The present invention relates to a computer system having a cache memory and in particular to a cache system appropriate for increasing the access speed to the cache memory.
Recently, as the processor operation frequency is increased, the ratio of the memory access latency against the processing time of a computer system as a whole is significantly increased. As a conventional method to reduce the memory access latency, a cache memory has been provided. The most ordinary cache memory includes a cache tag memory containing a tag and a valid bit added to the tag and a cache data memory having part of data of a memory-in-memory. The cache tag memory as one of the cache memory components stores information (tag) indication a data position in a memory belonging to the cache data memory so that the information is used to make a cache hit decision. At present, the LSI integration is increased and the cost required for production is reduced. Accordingly, the cache memory capacity in a computer system has been increased, which in turn is increasing the cache tag memory.
Increase of the cache tag memory capacity affect the cache access latency. If the cache tag memory capacity excess the size that can be mounted in an LSI, then the cache tag memory should be arranged outside the LSI. This increases the cache access latency due to an LSI external delay. Thus, it is necessary to reduce the access latency for the cache tag memory, thereby increasing the performance of a computer system.
For example, Japanese Patent Publication 9-293060 discloses a technique for effectively performing an access to a cache tag memory in a computer system to improve the performance. In this conventional technique, a plurality of processors share a main memory via a cache system to constitute a multi-processor system. Each of the cache systems has an address history issued from another cache system. If an address reported from anther cache system is contained in the address history, an unnecessary access to the cache tag memory is suppressed by a coherency transaction history control circuit. This facilitates the cache memory state decision processing for cache coherency control.
In general, a cache tag memory performs cache coherency control through management of four cache block states (MESI algorithm): Modified, Exclusive, Shared, and Invalid. The “Invalid” state (I) indicates that the cache block contains no valid data. The “Shared” (S) state indicates that the cache block contains data (clean data) identical to that in the main memory and this data is also present in another cache (shared). The “Exclusive” (E) state indicates that the cache block contains data (clean data) identical to that contained in the main memory and that this data is not present in the other caches. The “Modified” state (M) indicates that the cache block contains data (dirty data) which may differs from the main memory and that the data is not present in the other caches. That is, when data is written into a cache block, the data is handled as dirty data which may be different from the main memory.
In the aforementioned conventional technique, an access to a cache tag memory is suppressed if the state is “Shared” or “Invalid”. Accordingly, for example, when processing a task requiring frequent writing, each write updates the cache block state to “Modified”, which results in frequent access to the cache tag memory. Here, the access latency to the cache tag memory is a problem that cannot be ignored when considering the computer system performance. In the aforementioned conventional technique, access frequency to the cache tag memory when performing a transaction processing is determined by that upon a cache hit, one read process and one write process to the cache tag memory are required. Moreover, upon a cache miss, two read process and two write processes to the cache memory are required.
Thus, the conventional technique requires a large capacity of the cache tag memory and the cache tag memory is mounted outside an LSI having a cache control circuit and the like. When the access latency to the cache tag memory is increased, the latency required for a transaction processing of a computer system in increased.